Field of the Invention
The present invention relates to a method for providing bitline contacts in a memory cell array in which a plurality of bitlines is disposed in a first direction, the bitlines being covered by a silicon dioxide layer, a plurality of wordlines is disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells are disposed at the points at which the bitlines and wordlines cross each other.
The present invention can very advantageously applied to an EEPROM memory cell which is known from U.S. Pat. No. 5,168,334 to Mitchell et al. and which is also referred to as an NROM™ (nitride read only memory) cell which is further described in U.S. Pat. No. 5,966,603 to Eitan, U.S. Pat. No. 5,768,192 to Eitan, U.S. Pat. No. 6,133,095 to Eitan et al., and U.S. Pat. No. 5,963,465 to Eitan.
Such an NROM™ cell is a charge trapping memory device, which can be seen as a simple sub-micron MOS transistor whose gate oxide is replaced with a thin oxide-nitride-oxide (ONO) multi-layer stack, as can be seen from FIG. 1. In FIG. 1, reference numeral 1 denotes a substrate, for example of p-doped silicon. N+-doped bitlines 2a, 2b are disposed in a first direction, and they are covered by a thick silicon dioxide layer having a thickness of approximately 50 nm, also referred to as the bitline oxide 3. The word lines 4 made of polycide, a dual layer structure of tungsten silicide and polysilicon, are disposed in a second direction crossing the first direction. The second direction is, preferably, perpendicular to the first direction. The ONO multi-layer including a silicon dioxide layer 5, a silicon nitride layer 6, and a silicon dioxide layer 7, is disposed between the wordline 4 and the silicon substrate 1. A transistor having a channel 13 is formed between two adjacent bitlines 2a, 2b acting as source and drain electrode, the wordline 4 acting as the gate electrode and the ONO multi-layer acting as the gate isolator. The ONO multi-layer covers the channel area 13 of the transistor.
The intermediate layer of the ONO multi-layer stack, i.e., the nitride layer 6, is the retaining material for one or two distinguishable pockets of electrons, close to the bitline 2 junction edge.
For sake of simplicity, the concept of the NROM™ cell is described for the storage of one electron only. However, currently, the NROM™ cell is also applied for the storage of two electrons.
FIG. 2 shows a top view of a two-dimensional array of NROM™ cells, made of a crisscross of n+-doped bitlines 2 and wordlines 4. The location of the trapped electron is near the bitline junction edge, as shown in FIG. 1. Also shown is the memory cell 11 at the cross-section whose details are shown in FIG. 1. The programming operation of the NROM™ cell is done by Channel Hot Electron injection, which stores a nominal less than a thousand electrons in a lumped pocket close to the drain side of the cell. These electrons are located in localized states in the nitride layer.
An electron 8, for example, is injected and trapped by applying a higher potential to the first bitline 2a than to the second bitline 2b, as is indicated by the programming direction 10. Additionally, a sufficient voltage is applied to the wordline 4. For reading the electron 8, a higher potential is applied to the second bitline 2b than to the first bitline 2a, as is indicated by the reading direction 9. Additionally, a low voltage is applied to the wordline 4.
As is obvious, the potential difference applied for reading is lower than the potential difference applied for programming. Because a comparatively high voltage is applied to the wordlines for programming, the thickness of the spacer that covers the wordlines must be thicker than in other known memory devices such as a dynamic random access memory (DRAM) in order to avoid a breakthrough between neighboring wordlines or between a wordline and a bitline contact. In particular, typical voltages applied to the wordlines of NROM™ cells are approximately 12 Volts, whereas typical voltages applied to the wordlines of DRAM cells are 3 to 5 Volts.
Because the n+-doped bitlines 2 exhibit a considerable resistance, according to a standard cell architecture, metal lines are disposed on top of the memory cell array in arrays having a certain magnitude. These metal lines are also disposed in the first direction above the bitlines 2, and they are periodically connected to the underlying bitline through a contact. For example, every 8th or 16th memory cell has a contact to the metal line so as to reduce the bitline resistance. Because these metal lines usually are very thick, they place a further restriction upon the shrinkage of the memory cell size.
Conventionally, the contact between bitline and metal line can be provided by a method in which after the formation of the wordlines the whole memory cell array is covered by a boron phosphorous silicate glass as well as a silicon dioxide layer. Then, the silicon dioxide layer, the boron phosphorous silicate glass as well as the underlying bitline oxide are etched at predetermined positions that are, for example, photolithographically defined using a mask having a hole pattern so as to provide the contact holes. Thereafter, the contact holes are etched selectively with respect to the wordlines, especially the nitride spacer and nitride cap of the gate electrodes. Accordingly, the lateral extension of the contact holes is substantially defined by the spacing between neighboring wordlines. For this reason, such a contact is called a self-aligned contact (SAC).
Such a process involves two major disadvantages. On one hand, as explained above, the voltages applied to the wordlines of NROM™ cells are much higher than those applied to the wordlines of other known memory cells such as DRAM cells. Therefore, the nitride spacer and the cap nitride have to withstand much higher voltages and, thus, are made thicker. Consequently, the space between neighboring wordlines is reduced and the aspect ratio of the contact holes is much increased. In more detail, because the silicon dioxide layer usually has a thickness of 500 nm, contact holes having a very high aspect ratio of 10 to 15 have to be etched. Thus, it becomes very difficult to entirely etch the silicon dioxide layer, the phosphorous boron silicate glass as well as the underlying bitline oxide and, subsequently, fill the space between neighboring wordlines.
On the other hand, the etching time has to be appropriately adjusted to avoid too much etching of the nitride spacer. Accordingly, the process of etching the bitline oxide during the NROM™ fabrication is very critical. Insufficient etching times will result in an insufficient contact between bitline and bitline contact. However, for a better device performance, a low RC constant of the bitline contact is necessary to achieve a higher saturation current and a better signal detection. Moreover, excessive etching times will result in shorts between bitline contact and wordline that is a major problem in the fabrication of memory cell arrays.
By introducing a new etching gas, especially C5F8, having a higher selectivity of etching silicon dioxide deposited by the TEOS process with respect to silicon nitride, or by depositing a phosphorous boron silicon glass having a reduced thickness so that the stack that must be etched assumes a reduced height, the above problems can be partially solved. However, the results obtained still are not entirely satisfactory.
Another drawback arises because neighboring bitlines are insufficiently isolated from each other. Accordingly, there is a remarkable danger of punchthrough or leakage. Such a problem could be alleviated by introducing additional shallow trench isolation (STI) processes into the manufacturing process. However, the introduction of a conventional STI process into the hitherto known process of manufacturing an NROM™ cell array would lead to an increased cell size due to overlay requirements.
From T. H. Yoon et al., Symp. on VLSI Tech. Dig., 1999, p. 37, it is known to replace an SAC process by a so-called Pre Poly Plug process in which doped silicon is entirely deposited and patterned so as to provide a cell plug in a DRAM cell. However, as is obvious, a DRAM cell has a structure that is completely different from that of an NROM™ cell, and, in particular, there is no bitline oxide that has to be etched to provide a bitline contact.
U.S. Pat. No. 5,915,203 to Sengupta et al. discloses a method of producing deep submicron vias, wherein a blanket layer is formed on a dielectric layer and, then, photolithographically patterned. Subsequently, another dielectric layer is deposited and planarized, another blanket layer is deposited and photolithographically patterned so as to form via contacts.
Moreover, U.S. Pat. No. 5,815,433 to Takeuchi discloses a mask ROM device having a redundant circuit portion that is made of an MNOS structure acting as an EEPROM.